1. Field of the Invention
The present invention relates to a liquid crystal display (LCD) device and more particularly, to an array substrate for a liquid crystal display device and a manufacturing method thereof.
2. Discussion of the Related Art
Generally, a liquid crystal display (LCD) device includes two substrates that are spaced apart and face each other with a liquid crystal material layer interposed between the two substrates. Each of the substrates includes electrodes that face each other, wherein a voltage applied to each electrode induces an electric field between the electrodes and within the liquid crystal material layer. Alignment of liquid crystal molecules of the liquid crystal material layer is changed by varying the intensity or direction of the applied electric field. Accordingly, the LCD device displays an image by varying light transmissivity through the liquid crystal material layer in accordance with the arrangement of the liquid crystal molecules.
FIG. 1 is a cross sectional view of an array substrate for a liquid crystal display (LCD) device according to related art. In FIG. 1, a gate electrode 12, a gate line 14, and a gate pad 16 are formed on a transparent insulating substrate 10. The gate electrode 12 is elongated from the gate line 14, and the gate pad is located at an end portion of the gate line 14.
On the gate electrode 12, the gate line 14, and the gate pad 16 is formed a gate insulating layer 20, on which over the gate electrode 12, an active layer 22 and an ohmic contact layer 24 are sequentially formed.
On the ohmic contact layer 24 source and drain electrodes 32 and 34 are formed, and on the gate insulating layer 20 a data pad 36 having the same material as the source and drain electrodes 32 and 34 is formed. Though not shown in FIG. 1, on the gate insulating layer 20, a data line connected to the source electrode 32 and the data pad 36 is formed. The source and drain electrodes 32 and 34 form a thin film transistor T with the gate electrode 12.
Next, the source and drain electrodes 32 and 34, and the data pad 36 are covered by a passivation layer 40 that has first, second, and third contact hole for exposing the drain electrode 34, the gate pad 16, and the data pad 36, respectively.
Next, on the passivation layer 40, a transparent conductive material is deposited and patterned to form a pixel electrode 52, a gate pad terminal 54, and a data pad terminal 56. The pixel electrode 52 is connected to the drain electrode via the first contact hole 42, and a portion of the pixel electrode 52 overlaps with the gate line 14. The gate pad terminal 54 and the data pad terminal 56 are connected to the gate pad 16 and the data pad 36 via the second and the third contact holes 44 and 46, respectively.
The array substrate as explained above is manufactured by photolithographic processes using 5 masks, and the photolithographic process includes cleaning, deposition of the photoresist layer, exposure to light, development, etching, and so on. Therefore, if one photolithographic process step can be eliminated in the manufacturing of the array substrate, the manufacturing time and the cost can be reduced.